DFFREGSRH - MapleSim Help
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DFFREGSRH

Edge-triggered register bank with active-high reset and set and configurable output delay

 

Description

Connections

Parameters

Modelica Standard Library

Description

The DFFREGSRH component is an edge-triggered digital flip-flop register with active-high reset and set inputs and a configurable output delay. A positive transition (1-Trns) of the clock causes the input data to be latched and appear at the output after the specified delay.

The strength parameter specifies a map on logic signals. Its value consists of a symbol, , with  being one of the following: . The three subscripts define the map:

– 

A U always maps to a U.

– 

{X,Y,W,-} map to the first subscript ().

– 

{0,L} map to the second subscript ().

– 

{1,H} map to the third subscript (h).

For example,  means {X,Y,W,-} map to X, {0,L} map to 0, {1,H} map to H.

DataIn

Clock

Reset

Set

DataOut

*

*

*

U

U

*

*

U

*

U

*

*

*

1

1

*

*

1

0

0

*

*

1

X

X

*

*

X

X

X or U

*

*

0

X

X or U or 1 or NC

*

*

X

0

X or U or 0 or NC

*

X-Trns

0

0

X or U or NC

*

1-Trns

0

0

DataIn

*

0-Trns

0

0

NC

Symbol Definitions

Symbol

Definition

Clock Transition Definitions

Symbol

Definition

1-Trns

0-Trns

X-Trns

Connections

Name

Description

Modelica ID

Set input

set

Reset input

reset

Positive edge-triggered clock input

clock

Data input

dataIn

Data output

dataOut

Parameters

Name

Default

Units

Description

Modelica ID

High->Low delay

tHL

Low->High delay

tLH

 

Output strength

strength

 

Data width

n

Modelica Standard Library

The component described in this topic is from the Modelica Standard Library. To view the original documentation, which includes author and copyright information, click here.

See Also

Digital Components

Digital Registers

Electrical Library

 


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