The DFFREG component is an edge-triggered digital flip-flop register with an active-high reset and a configurable output delay. A positive transition (1-Trns) of the clock causes the input data to be latched and appear at the output after the specified delay.

The strength parameter specifies a map on logic signals. Its value consists of a symbol, $S_{\mathrm{xlh}}$, with $\mathrm{xlh}$ being one of the following: $\left\{\mathrm{X01}\,\mathrm{X0H}\,\mathrm{XL1}\,\mathrm{X0Z}\,\mathrm{XZ1}\,\mathrm{WLH}\,\mathrm{WLZ}\,\mathrm{WZH}\,\mathrm{W0H}\,\mathrm{WL1}\right\}$. The three subscripts define the map:

For example, $S_{\mathrm{X0H}}$ means {X,Y,W,-} map to X, {0,L} map to 0, {1,H} map to H.

Symbol Definitions

Symbol Definition $*$ $\mathrm{do\; not\; care}$ $U$ $\mathrm{L.\‵U\‵}$ $0$ $\mathrm{L.\‵0\‵}\mathrm{or}\mathrm{L.\‵L\‵}$ $1$ $\mathrm{L.\‵1\‵}\mathrm{or}\mathrm{L.\‵H\‵}$ $X$ $\mathrm{L.\‵X\‵}\mathrm{or}\mathrm{L.\‵W\‵}\mathrm{or}\mathrm{L.\‵Z\‵}\mathrm{or}\mathrm{L.\‵-\‵}$ $\mathrm{NC}$ $\mathrm{no\; change}$

	Clock Transition Definitions
	Symbol Definition 1-Trns $0\to 1$ 0-Trns $~\to 0\mathrm{or}1\to *\mathrm{or}X\|U\to X\|U$ X-Trns $0\to X\mathrm{or}X\|U\to 1$

The component described in this topic is from the Modelica Standard Library. To view the original documentation, which includes author and copyright information, click here.